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81	IEEE TRANSACTIONS ON COMPUTERS, VOL. 65, NO. 1, JANUARY 2016 Add to Reading List Source URL: www.eecs.qmul.ac.uk Language: English - Date: 2016-03-10 11:23:54 Cache CPU cache Centrality Distributed cache Draft:Cache memory
82	Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2013-10-10 09:58:44 Cache coherency MESI protocol Cache coherence Cache False sharing Draft:Cache memory CPU cache
83	Automatic Contention Detection and Amelioration for Data-Intensive Operations John Cieslewicz∗, Kenneth A. Ross†, Kyoho Satsumi, Yang Ye Department of Computer Science, Columbia University, New York NY (johnc,kar,ye Add to Reading List Source URL: event.cwi.nl Language: English - Date: 2010-08-10 12:02:01 Parallel computing Concurrency control MapReduce Thread Data-intensive computing CPU cache Non-blocking algorithm Concurrent data structure Synchronization Cray MTA Lock Linearizability
84	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
85	Computer Systems CS3650 http://www.ccs.neu.edu/course/cs3650/ Spring, 2016 Professor G. Cooperman Add to Reading List Source URL: www.ccs.neu.edu Language: English - Date: 2016-01-02 16:08:06 System calls Application programming interfaces Concurrent computing Parallel computing Computer architecture Xv6 Thread CPU cache Fork POSIX Unix Multi-core processor
86	Moneta: A High-performance Storage Array Architecture for Next-generation, Non-volatile Memories Adrian M. Caulfield Arup De Rajesh K. Gupta Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2011-04-30 02:41:36 Computer memory Non-volatile memory Computer architecture Computer storage devices Computer storage media Solid-state drive IOPS Direct memory access PCI Express Flash memory CPU cache Noop scheduler
87	An Operational Semantics of Cache Coherent Multicore Architectures∗ Shiji Bijo, Einar Broch Johnsen, Ka I Pun, and S. Lizeth Tapia Tarifa University of Oslo, Norway {shijib, einarj, violet, sltarifa}@ifi.uio.no Add to Reading List Source URL: einarj.at.ifi.uio.no Language: English - Date: 2016-01-07 10:39:37 Cache coherency Parallel computing Computer architecture Computer memory computing CPU cache MSI protocol Coherent cache Cache MESI protocol Multi-core processor Draft:Cache memory
88	Comparative analysis between QuickThread and Intel® Threading Building Blocks (TBB) Copyright © 2009 QuickThread Programming, LLC www.quickthreadprogramming.com Add to Reading List Source URL: www.quickthreadprogramming.com Language: English - Date: 2012-05-03 14:20:38 Parallel computing Concurrent computing Application programming interfaces Software design patterns Central processing unit Threading Building Blocks Thread OpenMP Monitor CPU cache C++11 Multithreading
89	Flash Caching on the Storage Client David A. Holland, Elaine Angelino, Gideon Wald, Margo I. Seltzer Harvard University Abstract Flash memory has recently become popular as a caching Add to Reading List Source URL: www.eecs.harvard.edu Language: English Computer memory Computer architecture Non-volatile memory Cache Flashcache Solid-state drive ReadyBoost Flash memory Random-access memory Thrashing Write buffer CPU cache
90	Automatic Mapping of Parallel Applications on Multicore Architectures using the Servet Benchmark Suite Jorge Gonz´ alez-Dom´ınguez∗, Guillermo L. Taboada, Basilio B. Fraguela, Mar´ıa J. Mart´ın, Juan Touri˜ no Add to Reading List Source URL: gac.udc.es Language: English - Date: 2012-03-15 09:04:50 Parallel computing Multi-core processor Message Passing Interface OpenMP CPU cache Thread Supercomputer Computer cluster Partitioned global address space Symmetric multiprocessing Multiprocessing Benchmark

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